The I/O Processor Board�s signal line used to check the ability of the 280 CPU to write a value out to the board edge connector and correctly read it back. Also, the 9-Channel�s strobe signal derived from Control Processor control lines; used for gating probe and board I.D. data through the Status Monitor. The acquisition board T clock falling edge indicator; active when the probe C/Q line goes from a logic 1 to logic 0. The Trigger�s load signal for control RAMS containing sequence commands for true and false conditions. The 9-Channel�s threshold write signal derived from Control Processor control lines; used when setting the 9-Channel�s threshold setting. The 18-Channel�s threshold write signal derived from Control Processor control lines; used when setting the 18-Channel�s threshold setting. The 18-Channel�s timebase selection programming strobe. The Display Board�s timing diagram data signal carrying serial data to the Timing Diagram ROM. Also the 9-Channel�s signal derived from Control Processor control lines; used as a write strobe for loading timing control values. The Display Board�s timing mode signal used to indicate the display is currently generating timing diagrams. Trigger Position signals from the trigger circuitry located on the Control Processor to the Trigger Board; indicates zero detection (where zero is the trigger location). Trigger position indicator 1 and 2 ripple clock signals from the Trigger Board to the Control Processor Board; used to clock upper 8 bits. The Trigger�s master reset signals for the Trigger Position Indicator counters. The Trigger�s control signal used to specify glitches on the Test Pattern Generator. The Trigger�s control signal used to specify either T1 (true) or 12 MHz (false) as the base clock for the Test Pattern Generator. The Trigger�s T1 signal for the Test Pattern Generator clock in TPG modes 2 and 3. The Trigger�s TPI 1 and 2 prescale readback.
