Pin Name DOUT FSX EFLG TEST EMPH MUTEL MUTER LVDD LCHO LVSS RVSS RCHO RVDD
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Description Digital OUT output pin. (EIAJ format) Output pin for the 7.35kHz synchronization signal divided from the crystal osillator. C1 C2 error correction monitor pin. Test input pin. Must be connected to OV. Emphasis pin. Which becomes an input pin after reset and can becontrolled externally. This becomes an emphasis monitor pin under control by command. L channnel mute output pin. R channel mute output pin. L channel power supply pin. (2000pF or more path controller to be inserted at a point nearer to the pin between this pin and GND) L channel output pin. L channel ground pin, Must be connected to 0V. R channel ground pin, Must be connected to 0V. R channel output pin. R channel power supply pin. (2000pF or more path controller to be inserted at a point nearer to the pin between this pin and GND)
XVDD XIN XOUT XVSS ASLRCK ASDACK ASDFIN LRSY DATACK DATA 16M SFSY SBSY PW SBCK CE CL DI DO *INT *WRQ *RES DRF
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Crystal oscillator power supply pin. (2000pF or more path controller to be inserted at a point nearer to the pin between this pin and GND) Connections for a 16.9344MHz crystal oscillator pin. Crystal oscillator ground pin. Must be connected to 0V. L/R clock input pin. (Must be connected to 0V when unused) Bit clock input pin. (Must be connected to 0V when unused) L/R channel data input pin. (Must be connected to 0V when unused) L/R clock output pin. Bit clock output pin. L/R channel data output pin. 16.9344MHz output pin. Subcode frame synchronization signal output pin. This signal falls when the subcode is in the standby state. Subcode clock synchronization signal output pin. Subcode P, Q, R, S, T, U and W output pin. Subcode readout clock input pin. Chip enable signal input pin. Data transfer clock input pin. Data input pin. Data output pin. Interruption signal output pin. Interruption signal output pin. Reset input pin. This pin must be set low briefly after power is first applied. Focus ON detect pin.
