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3. ACTUAL CIRCUIT
In the actual circuit, the resonant capacitor is split into two as shown in Fig. 10-7. One, C440, is inserted between the collector of the H. OUT transistor and ground and another C444 inserted between the collector and emitter. In Fig. 105, C440 is expressed as C1 and C444 as C2, and the resonant current path for the flyback period is shown by arrows. In a conventional circuit, when brightness of a picture tube varies, high voltage current varies and the high voltage also varies. As a result, horizontal amplitude also varies. However, in this circuit, the horizontal amplitude variation can be suppressed to near zero if the high voltage current varies with variation of the high voltage. When the scanning period completes, the energy stored in the deflection yoke L DY is transferred to the resonant capacitor in a form of current I Y. In this case, the current is split into two; IY1 passing through C1, C3 and IY2 passing through C2. In the same way, the energy stored in the primary winding of the FBT is transferred to the resonant capacitor in the form of IP. In this case, the current (path) is also split into two; I P1 passing through C1 and IP2 passing through C2, C3. Concequently, the current differences between IY1 and IP2 (IY1-IP2) passes through C3. When the high voltage current IH reduces with a dark picture, the current IP in the primary circuit decreases, so IP1 and IP2 also decrease. However, a current flowing into (IY1IP2) increases as IP2 decreases. As a result, the pulse developing at the point B increases and the voltage Vm at Csm also increases as shown in Fig. 10-8. That is, when a dark picture appears, the voltage across S-curve capacitor CS increases as shown in Fig. 10-8, the high voltage rises, and the horizontal amplitude is going to decrease. But, as VS increases, the deflection yoke current increases and this works to increase the horizontal amplitude. Accordingly, if the brightness of picture changes, the horizontal amplitude is maintained at a constant value. This is one of the fine features the circuit has.
VB
IP2 IY1 H. OUT IY1 IY2 IY C2 Lm C3 Csm Vm LDY CS IP
IP1 C1
IP2
FBT
IH
VS VB
Fig. 10-5
VS
0 Vm
Fig. 10-6
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