AIWA NSX500
Manual de Servicio

Pin No. 77 78 79 80

Pin Name DATO XLTO CLKO MIRR

I/O O O O I Serial data output to SSP.

Description

Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP. Mirror signal input. Used when the number of tracks is 128 or more for the 2N-track jump and M track move of the auto sequencer.

Notes) � The 64-bit slot is an LSB first, two�s complement output, and the 48-bit slot is an MSB first, two�s complement output. � GTOP is used to monitor the frame sync protection status. (High: sync protection window open.) � XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection. � XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. � GFS goes high when the frame sync and the insertion protection timing match. � RFCK is derived from the crystal accuracy, and has a cycle of 136µ. � C2PO represents the data error status. � XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.

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