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Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 to 77 78 to 80
Pin Name UNIREQ UNICKI UNISI UNISO MD-CKO MD-SI NCO SENS CC-XINT LIMIT-IN EJT-KEY ERROR-PWM MD-RST BU-IN BUS-ON SQSY C-SW MD-LAT MD-ON DEEMP A-MUTE NCO TSTCKO TSTSO TSTMOD VCC NC
TOUT0 to TOUT3
I/O O I I O O I O I I I I O O I I I I O O O O O O O I � I O I/O
Function Data request signal output terminal (for SONY bus) �H�: request on Not used (open) Serial data transfer clock signal input from the master controller (IC500) (for SONY bus) Serial data input from the SONY bus interface (IC504) Serial data output to the SONY bus interface (IC504) Serial data transfer clock signal output to the CXD2652AR (IC301) and CXA2523R (IC302) Reading serial data signal input from the CXD2652AR (IC301) Not used (open) Internal status (SENSE) input from the CXD2652AR (IC301) Interrupt status input from the CXD2652AR (IC301) Detection input from the sled limit-in detect switch The optical pick-up is inner position when �L� Eject request signal input terminal �L�: eject on Not used (fixed at �H�) PWM error monitor output terminal (C1and ATER is output when test mode) Not used (open) Reset signal output to the D/A converter (IC101), CXD2652AR (IC301) and BH6511FS (IC303) �L�: reset Battery detect signal input from the SONY bus interface (IC504) and battery check circuit �H�: battery on SONY bus on/off control signal input from the master controller (IC500) �L�: bus on Subcode Q sync (SCOR) input from the CXD2652AR (IC301) �L� is input every 13.3 msec Almost all, �H� is input Inputs the disc loading start or disc eject completion detect switch detection signal �L�: When start or eject completed of the disc loading operation Serial data latch pulse signal output to the CXD2652AR (IC301) and CXA2523R (IC302) Power supply on/off control signal output of the MD mechanism deck section main power supply �H�: power on Emphasis on/off control signal output to the D/A converter (IC101) �H�: emphasis on Audio muting on/off control signal output to the master controller (IC500) �H�: muting on Not used (open) Output of clock signal for the test mode display Not used (open) Output of data for the test mode display Not used (open) Setting terminal for the test mode �L�: test mode, �H�: normal mode Power supply terminal (+5V) Not used (fixed at �H�) Output of the 4�8 matrix test keys Not used (open) Not used (open) Input of the 4�8 matrix test keys (�L� is always output, except in test mode)
TIN0 to TIN2
*1 Loading motor (M903) control Operation Terminal LOAD (pin 6) EJECT (pin 7) IN �H� �L� OUT �L� �H� BRAKE �H� �H� STOP �L� �L�
� 90 �
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