PANASONIC EBGD67
Manual de Servicio

TECHNICAL DESCRIPTION

4.5.3

Power On / Off Control

The power on sequence can begin when VBAT >2.6 V or VBACKUP >2.6 V. In this state IOTA (U620) is in Power On Condition and internal supply UPR is active. RESPWRONZ signal to CALYPSO (U642) is released high. If IOTA is in the Power On Condition, one of following conditions start the Power Up sequence. � � � � Power key is pushed for more than 30 ms. RPWON input goes high to low for more than 30 ms (e.g. accessory is connected). EXTPWR voltage is higher than (VBAT+0.4) V. CALYPSO RTC ALARM signal goes high.

The Power Up sequence is as follows: 1. 2. 3. 4. 5. 6. IOTA internal band gap reference is activated. If VBAT < 3.2 V after a timeout of 51.2 ms Power Up sequence is aborted. All regulators (VRDBB, VRMEM, VRRAM, VRIO, VRABB & VRRTC) are enabled. Power Up status bit and internal Reset bits are set. ONNOFF signal is set to activate CALYPSO. ARM in CALYPSO starts running software using 32 kHz clock, and also starts 26 MHz clock.

The following Power Down sequence can only be started by CALYPSO setting the DEVICE_OFF bit in IOTA or, in emergency case, when VBAT < 2.7 V (or VBAT < Vbackup & VBAT < 2.8 V): 1. 2. 3. 4. 5. If emergency case, INT1 is set low by IOTA. IOTA starts an internal 150 µs watchdog timer to allow CALYPSO to shutdown. ONNOFF signal is reset to deactivate CALYPSO. All regulators (VRDBB, VRMEM, VRRAM, VRIO, VRABB & VRRAM) are disabled. IOTA internal band gap reference is deactivated.

4.5.4

Power Source Detection Failure

The SIM card contains EEPROM. If the power fails (i.e. battery removal) while the SIM is active, the SIM may corrupt its memory as the supply voltage drops out of specification. There is sufficient time between Low Voltage Alarm (LVA) detection and IOTA switch-off for the software to cease writing to the SIM to prevent corruption without the need for any interrupt signal from IOTA.

4.5.5

Voltage Regulation

The voltage regulators for I/O and memories have a nominal output of 2.8 V, and are designed to provide a minimum 2.7 V output over all load, transients and temperature conditions. Each power source is specified as follows. � VRDBB: Power supply for the CALYPSO (Lead Mega Module) LMM block. Voltage Current Dropout Supply 1.8 V ±0.15 V 120 mA max. 100 mV max (load max) VBAT

This power supply provides the power for CALYPSO internal RAM, ASIC modules, LMM and ARM Blocks, and is selectable from 1.18 V, 1.4 V and 1.8 V. � VRIO: Power supply for IOTA ASIC I/O and CALYPSO. Voltage Current Dropout Supply 2.8 V ±0.15 V 100 mA max. 100 mV max (load max) VBAT

This is the main power supply for the baseband digital sections (I/O and LCD) and some analogue sections. It is also used for the digital I/O ring on both CALYPSO and IOTA. MMCD020801C8 Service Manual Section 4 � 15 � Issue 1 Revision 0