SONY BVM-D32E1WA
Manual de Servicio

� R Signal Matrix Circuit The Y signal and R�Y signal are added at Q115 to form the R signal. � G Signal Matrix Circuit At IC307, the R�Y signal and B�Y signal are inverse-amplified and added via IC306 (gain control amplifier). This signal is added to the Y signal at Q315 to obtain the G signal. The mixing rate is determined by R358, 359, and 361, and the R�Y and B�Y GAIN are finely adjusted. � B Signal Matrix Circuit The Y signal and B�Y signal are added at Q515 to form the B signal. 6. RGB Switch Switches between the RGB signal and R,G,B signals from the matrix circuit. 7. Clamp Circuit (2) The voltage of the BLACK pulse of the R signal is sample-held at IC110. At IC113 (1/2), this voltage and the GND level are compared to control the DC bias of the R signal amplifier (Q120 to Q122). As a result, the pedestal level of the R signal is fixed at the GND level. The same is performed for the G and B signals. 8. Half Blanking The video signal is half-blanked at the timing of the CHAR BLK signal. The half-blanking level is switched by the HALF LEVERL SW. 9. 100 IRE Pulse, SET UP Pulse Insertion Circuit To adjust the contrast, the 100 IRE pulse and SET UP pulse are alternately inserted into the horizontal blanking period of the R,G,B signals. For the R signal, the 100 IRE pulse and SET UP pulse are inserted at IC112 (3/3). The level of the 100 IRE pulse is set by the R100 IRE voltage. The level of the SET UP pulse is set by the R SET UP voltage. These two voltages are switched by WHITE INSERT P at IC110 (3/3), passed through IC112 (2/3), and input to IC112 (3/3). At IC112 (2/3), the half-blanked video signal is inserted. The same is performed for the G and B signals. 10. Blue Only Switch During the blue only mode, the B signal is output instead of the R signal at IC115 (1/3), and the B signal is output instead of the G signal at IC315 (1/3). 11. Contrast, Bright Adjustment Circuit The R signal is adjusted for its contrast at IC116 (gain control amplifier). The R signal output from IC116 is input to IC115 (2/ 3) and the voltage of the 100 IRE pulse is sample-held. At IC117 (1/2), this voltage and the CONT voltage are compared to control the gain of IC116. As a result, the 100 IRE pulse voltage becomes equivalent to the CONT voltage. Consequently the contrast can be adjusted by varying the CONT voltage. The R signal output from IC116 is also input to IC115 (3/3). In this IC, the voltage of the SET UP pulse is sample-held. This voltage and the GND level are compared at IC117 (2/2) to control the DC bias of IC112. As a result, the pedestal level of the R signal is fixed at the GND level. At the same time, the DC bias of IC116 is controlled by the BRT voltage to perform bright adjustment. The BRT voltage is generated in IC701 (1/3) by switching the BRIGHT voltage and BRT CENTER voltage in the pulse (100 IRE pulse, SET UP pulse) insertion period and in other periods. The same is performed for the B and G signals.

6-2

BVM-D32E1WA/D32E1WE/D32E1WU