¶ Pin Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 DVDD1 CE DO DI CL PSC1 PSC2 WAIT INT TEST7 DVSS1 WE RAS A0 A1 A2 A3 A4 A5 A6 A7 DB0 CAS DB1 OE DB2 DB3 CB TEST8 AVSS1 I/O I I O I I I � I O I I O O O O I � O O Function
Test input. Connect to GND during normal operations. Test input. Connect to GND during normal operations. Test output. Test input. Connect to GND during normal operations. Test input. Connect to GND during normal operations. Test input. Connect to GND during normal operations. Digital power supply (+5V) Serial input/output data control input Serial data output Serial data input Serial data input/output clock input Serial input monitor signal output Command monitor signal output Serial input wait signal output (For bit map) Serial input wait signal output (For sprite) Test input. Connect to GND during normal operations. Digital GND DRAM write enable signal output DRAM line address strobe signal output
Pin Name AVDD1 VIDEO1 BIAS VIDEO2 BFP LINE FSCIN VSYNC TEST9 YS CSYNC 4FSC2 TEST10 TEST11 TEST12
I/O �
Function
Analog power supply
O Video (Luminance) signal (analog) output (DAC output) O Connects ripple removal capacitor O Video (Chroma) signal (Analog) output (DAC output) O Burst signal output timing flag output
Line number selection input (During non-interlace)
O Vertical sync signal output
Test input. Connected to GND during normal
I
operations (Pull down resistor incorporated)
O Superimpose control output O Composite sync signal output
Superimpose external clock input
I
(Feedback resistor incorporated)
O Test output O Test output I
Test input. Connected to GND during normal operations (Pull down resistor incorporated) External control input for superimpose during PAL
I/O DRAM address (A0) output (Input switched during test) I/O DRAM address (A1) output (Input switched during test) I/O DRAM address (A2) output (Input switched during test) I/O DRAM address (A3) output (Input switched during test) I/O DRAM address (A4) output (Input switched during test) I/O DRAM address (A5) output (Input switched during test) I/O DRAM address (A6) output (Input switched during test) I/O DRAM address (A7) output (Input switched during test) I/O DRAM data (D0) input/output O
DRAM row address strobe signal output
52 53 54 55 56 57 58
PALID HRESET FSCO VRESET INIT RESET N/P1
I I O I I I I
(Pull up resistor incorporated)
External horizontal sync timing control input Sub carrier clock output NTSC: 3.579545 MHz PAL: 4.433619 MHz External vertical sync timing control input System initial signal input System reset signal input NTSC/PAL select input (RGB encoder) Hi: NTSC ; Lo: PAL NTSC/PAL select input (Decoder)
I/O DRAM data (D1) input/output O
DRAM read enable signal output
59
N/P2
I
Hi: NTSC ; Lo: PAL Superimpose ON/OFF control input Hi: Superimpose ON PAL crystal resonator (4Fsc=17.734476 MHz) NTSC crystal resonator connection terminal
I/O DRAM data (D2) input/output I/O DRAM data (D3) input/output I O �
Lo: Normal mode, Hi: Color bar output (Pull down resistor incorporated) Test output Analog GND
