IC DESCRIPTION IC, CXD2652AR
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin Name MNT0 MNT1 MNT2 MNT3 SWDT SCLK XLAT SRDT SENS XRST SQSY DQSY RECP XINT TX OSCI OSCO XTSL DVDD DVSS DIN DOUT ADDT DADT LRCK XBCK FS256 DVDD A03 A02 A01 A00 A10 A04 A05 A06 A07 A08 A11 I/O O O O O I I I O O I O O I O I I O I � � I O I O O O O � O O O O O O O O O O O Monitor output terminal. Monitor output terminal. Monitor output terminal. Monitor output terminal. Microprocessor serial interface data input. Microprocessor serial interface shift clock input. Microprocessor serial interface latch input. Latched at falling down edge. Microprocessor serial interface data output. The terminal which outputs internal status in accordance with the address of the microprocessor serial interface. Reset input. L: reset. Disc sub code Q sync/ADIP sync output. Subcode Q sync output of U-bit CD or MD format when the DIGITAL IN source is CD or MD. Laser power selection input. H: Recording power, L: Playback power. Interrupt request output terminal. L is output when interrupt status is generated. Record data output enable signal input terminal. H: enable. Crystal oscillator circuit input terminal. Crystal oscillator circuit output terminal. (Inverted output of OSCI). OSCI terminal input frequency selection. H: 512 Fs (22.5792 MHz), L: 1024 Fs (45.1584 MHz). Digital Power Supply. Digital GND. Digital audio interface signal input. Digital audio interface signal output. Analog recording signal input terminal. (External A/D converter output is connected to this terminal). RECORD monitor output/decode audio data output. LRCK (44.1 kHz) output terminal to external audio block. Bit clock output (2.8224 kHz) output terminal to external audio block. 256 Fs output. (11.2896 MHz). Digital power supply. Address output to external DRAM. Address output to external DRAM. Address output to external DRAM. Address output to external DRAM. Address output to external DRAM. (Not used). Address output to external DRAM. Address output to external DRAM. Address output to external DRAM. Address output to external DRAM. Address output to external DRAM. Address output to external DRAM. Description
