TOSHIBA TLP670EF/UF
Manual de Servicio

2-3. Operation at Y/Pb/Pr Signal and HDTV Signal Input
Y/Cb/Cr signal (DVD player output) or HDTV signal enters from PB001 and reaches the A/D converter (QD100) for Y/Cb/Cr (Y/Pb/Pr) signal after passing through the low pass circuit. The A/D converter develops 16 bit signal of 8bit Y signal + 8bit Cb/Cr (Pb/Pr) and enters the scaller IC through the selector for the signal and that from the video decoder inside QD405. The process following to the scaller IC is the same as that of the video signal process. The process relating to the sync process at Y/Cb/Cr signal (DVD player output) input (clock generation) is carried out by the video decoder and the clock generation at HDTV signal input is by the A/D+PLL (QD300).

2-5. Camera Overlay Signal
The camera overlay signal usually enters the A/D converter for Y/Cb/Cr signal (Y/Pb/Pr) through an exclusive connector in the same way as that of camera input. The A/D converter output enters QD405 and the red and blue components of the signal are extracted by the level slice circuit. Thus processed signal is converted into the signal synchronizing with the LCD panel output timing by using a memory (QD46). Then the signal is overlapped with the on-screen signal and the signal overlapped is fed to the on-screen signal input of the scaller IC, and overlapped with the main video output signal. At this time, the clock generation for overlay signal input system is carried out by the PLL circuit exclusive for the overlay. As described above, the A/D converter for Y/Cb/Cr (Y/Pb/ Pr) signal is used for the overlay signal input, so the signal which is usually processed by the A/D converter for Y/Cb/Cr (Y/Pb/Pr) signal, that is, Y/Cb/Cr signal (DVD player output), cannot be overlaid at the HDTV signal input.

2-4. Camera Input Operation
A camera input enters the A/D converter for Y/Cb/Cr (Y/ Pb/Pr) signal through an exclusive connector and is processed as a Y/Cb/Cr signal input. The camera signal is a Y/Cb/Cr signal of fh=11.8 kHz and fv=15 Hz. The clock generation is carried out in the A/D+PLL (QD300).

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