SONY HKPF-103M
Manual de Servicio

Section 5 Block Diagrams
5-1. Circuit Description
(1) DIF-103 Board (Input side) The DIF-103 board mounts a cable equalizer and PLL IC as the circuit block on the input side. The provided HD SDI signal to CN11 is automatically equalized (cable-compensated) for a cable loss of maximum 100 m (5C-FB) using a cable equalizer (A12). The equalized serial data is identified into the binary data using the comparator in the A12 and is distributed to the clock extractor PLL (IC13) in the next stage. In the PLL, a clock signal is extracted to lock in phase the inside VCO to the restored serial data to the binary data. After the input signal is latched using the extracted serial clock and then converted the data and the clock into ECL level in pairs are provided to the DPR-151C board (processor board) in the latter stage. The PLL has the detecting function of the input signal or not. When a signal does not input, the HD SDI output is performed to turn off via the CPU of the DPR-151C board. When an input situation changes from no signal to signal input, the VCO (X1) is mounted for free-run so that the PLL pull-in process is quickly executed. (2) DIF-103 Board (Output side) The provided serial data from the DPR-151C board is latched by IC1 in the entrance stage and is provided to the cable driver (IC10, IC11 and IC12) distributing of IC4, IC7 and IC8. RV1, RV2 and RV3 are the output amplitude adjustment volumes. Two signals (inverted and non-inverted signals) are provided from the cable driver, are provided as each HD SDI output signal and six HD SDI output signals in all are obtained. (3) DPR-151C Board The serial data and the clock from the DIF-103 board are provided to the serial-to-parallel converter of IC100 and are converted into the 20-bit parallel data of 74 MHz rate. IC101 is a format decoder and is extracted each timing signal (F, V, and H) from the received video timing standard code (EAV/SAV). HKPF-103M has an internal PLL circuit that is used VCXOs and reproduces a stable clock signal using the PLL circuit. The PLL circuit consisting of a timing generator (IC300) and VCXOs (X302 and X303) is generated the parallel
HKPF-103M MM

clock that is locked to the extracted H signal by IC101. The used VCXOs (X302 and X303) in this block are automatically selected 74.25 MHz or 74.25 MHz/1.001 according to the field frequency of the received serial data. The 20-bit parallel data is carried out the re-timing of a clock by IC104 and is provided to the parallel-to-serial converter IC of IC202 together with a 74.25 MHz or 74.25 MHz/1.001 clock. The parallel-to-serial converter IC has an internal phase comparator for serial clock regeneration and is re-generated a 1.485 GHz serial clock by combining the internal phase comparator and the external VCO (OSC200). The serial data and the clock signal are provided to the DIF-103 board in pairs. HKPF-103M has an internal CPU (IC604), is initialized each device and judges the operating format and controls the status output. HKPF-103M is interfaced with the DIP switches and the LEDs through IC701 (parallel interface unit), is carried out the settings of the switches and the displays of LED indicators through CPU. HKPF-103M corresponds to the multi-format, can be automatically or manually selected the objective format by S703-3. In the manual selection, the format is specified by the S702 rotary switch. On the other side, in the automatic format selection, the format that is corresponded with the input HD SDI signal within the format according to the selected bit by S704 and S705, is selected and is set. The DPR-151C board mounts the switching regulators of the +3.3 V, +1.2 V and _2 V and the series regulator of the +2.5 V as a power supply circuit. These voltages required as the power supply for ASIC are generated by DC-DC converting the +5 V and _5 V voltages that are supplied from the mother board of PFV-HD50/HD300.

5-1 (E)