SONY DVA-P1100
Manual de Servicio

1-4. Circuit Operation

1-4. Circuit Operation
1-4-1. DVA-A1100
The DIO-56 board consists of the following circuit blocks: 1. Digital audio interface 2. LTC reader/generator 3. PCI-to-local-bus bridge 4. PLD & SRAM 1. Digital audio interface (IC1, IC2, IC3, and IC4) This board uses a digital audio receiver (IC1, IC2) and digital audio transmitter (IC3, IC4) as the digital audio interface IC. The DI1 (CH1/2) signal that is input through the D-sub 25 pin connector is converted to a serial signal of 64 bits/sample by IC1, and input to the digital audio flow controller (IC5) and the SRAM (IC7 to IC9). The DI2 (CH3/4) signal is also converted to a serial signal of 64 bits/sample by the audio receiver (IC2) in the same way, and input to the digital audio flow controller and the SRAM. In this board, the DI1 input signal is the master of the clock, so the digital audio receiver (IC1) generates 256 Fs and FSync from the DI1 input. These clock signals are sent to the FPGA and become the master clock of all operations. Also, they are sent to the other digital audio interface ICs via the PLD & SRAM. The 64 bits/sample serial signal that is output from the PLD & SRAM is converted to the digital audio signals DO1 (CH1/2) and DO2 (CH3/4) by the digital audio transmitter (IC3, IC4). The signals that should be added to the digital audio signal, such as the control bit, etc., are set from the data bus of the IC1, IC2, IC3, and IC4. The bus is connected to the PCI-to-local-bus bridge, and receives/ sends data from/to the PC applications via the PCI bus.

2. LTC reader/generator (IC16, IC14, and IC15) This block consists of the following : LTC reader/generator (IC16) Input/output buffer (IC14, IC15) The time code signal TCI/TCO that is input via the D-sub 25 pin connector is connected to the LTC reader/generator (IC16) via the input/output buffer (IC14, IC15). Receiving/sending of the time code data and controls are performed by the data bus IC16. This bus is connected to the PLD & SRAM, and is used for processing that is synchronized with the time code, in the PLD & SRAM. Receiving/sending data and controls with the PC applications are performed through the bus that is connected between the PLD & SRAM and PCI-to-local-bus bridge using the PLD & SRAM.

1-2 (E)

DVA-A1100/P1100/R1100