SONY CVC-1000
Manual de Servicio

1-3. MB-829 BOARD
This board consists of the timing pulse generator section that controls the CCD, V driver clock generator section, electronic shutter control section, Selective Vertical Readout control section, etc. a. b. c. d. e. f. Timing pulse generator section Clock drive circuit for CCD vertical transfer System clock generator section TRG shutter control section Selective vertical readout control section Data Valid signal control section

a. Timing pulse generator section The TG IC (IC5) generates various timing pulses necessary for driving the CCD, by using 49 MHz clock input from the system clock generator section and the HD and VD signals from the SUB TG (IC4). The timing pulses generated by IC5 are as follows: RG : Clock for CCD reset gates H1, H2 : Two-phase clocks for CCD horizontal transfer XV1 to XV3 : Three-phase clocks for CCD vertical transfer XSG : Pulse for reading out charges from the photosensor section XSHP, XSHD : Sampling pulses for correlative doublesampling XCPOB : Clamp pulse for DC restoration PBLK : Preblanking pulse b. Clock drive circuit for CCD vertical transfer The V driver (IC3) receives XV1 to XV3 and XSG from IC5, and outputs the V1 to V3 pulses by internally adding XSG onto XV2 and XV3. On that occasion, IC3 serves as a driver for the V1 to V3 pulses to directly drive the CCD. It also serves as a driver for the VSUB pulse generated at IC4. c. System clock generator section It consists of the quartz oscillation circuit, whose oscillation frequency is 49.0909 MHz. The system clock signal is input to IC5, where the signal is divided into 24.5454 MHz CL pulses, which are output from IC5 to IC4.

d. TRG shutter control section IC4 generates various pulses to enable TRG shutter control, by entering TRG and EXT-VD from outside and a 24 MHz clock signal from IC5. The pulses generated from IC4 are as follows: SUB : Pulse for the electronic shutter, which is generated in synchronization with the rising edge of the trigger (TRG) HDI : Horizontal synchronization signal for TG input, which is to be modulated in synchronization with the falling edge of the TRG (S1 = L) Continuous horizontal synchronization signal (S1 = H) VDI : Vertical synchronization signal for TG input, which is to be modulated in synchronization with the falling edge of the TRG (S1 = L) Continuous vertical synchronization signal (S1 = H) The HDI and VDI outputs can be switched as mentioned above with S1. With S1 set to L, TRG shutter mode is established, and with S1 set to H, NORMAL mode is established. In TRG shutter mode, IC4 receives SCPOB and PBLK from IC5, and modulates and outputs them to the PR-247 board. e. Selective Vertical Readout control section The Selective Vertical Readout (SVR) function is controlled by entering SVR0 to SVR2 external control signals to IC4. With the SVR function, a selected range of lines is read out according to the SVR0 to SVR2 signal setting, as indicated below:
SVR2 0 0 0 0 1 1 1 1 SVR1 0 0 1 1 0 0 1 1 SVR0 0 1 0 1 0 1 0 1 Lines to be read out All lines 68 to 488 (420 lines) 128 to 488 (360 lines) 188 to 488 (300 lines) 248 to 488 (240 lines) 308 to 488 (180 lines) 368 to 488 (120 lines) 428 to 488 (60 lines)

f. Data Valid signal control section The Data Valid signal is output from IC4 Pin 78 by setting S2 to L. The Data Valid signal, which expresses a video period using the H and V rates, also serves as a WEN pulse. The Data Valid signal is output only in TRG shutter mode.
CVC-1000

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