The HFL (high frequency level) signal is used to judge whether the main beam is positioned on the pit or on the mirror.
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Sled servo off control input. I CLV error signal input from the DSP, RF output. RFSM pin. Sets the RF gain and the EFM signal�s 3T compensation constant together with the
cvCv+ I
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RFSM RFS-
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43 44 45 SLC SL1 DGND FSC 1471 48 49
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The SLC (slice level control) signal is output to control the DSPS data slice level of the RF waveform.
o I � o I � 0 I I I I I I I Input to control the DSPS data slice level. Ground of digital signals. Output for the focus search smoothing capacitor. The TBC (tracking balance control) signal sets the EF balance variation range. Not connected. Dsic defect detection output. Reference clock input. 4.23 MHz is input from the DSP. Microprocessor command clock input. Microprocessor command data input. Microprocessor chip enable input. DRF (detect RF) is an output to detect the RF level. The FSS (focus search select) signal switches the focus search modes (+/-search/ 1 1
TBC NC DEF CLK CL DAT CE DRF 55 FSS
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VCC2
+search with respect to the reference voltage). � �I \ O � � � o I I I \ I I VCC of servo and digital circuits. For the connection of bypass capacitor for the reference voltage. Reference voltage output. Sets the time constant for disc defect detection. For the connection of a capacitor to hold the RF signal peak. For the connection of a capacitor to hold the RF signal bottom. APC circuit output. APC circuit input. VCC of RF signal circuits. I
