VESTEL 11AK33
Manual de Servicio

can be forced by the I 2 C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The horizontal output signal is generated by means of a second loop, which compares the phase of the internal oscillator signal with the phase of the incoming flyback pulse. The time-constant of this loop is connected externally and can be used as input for a dynamic horizontal phase correction. To obtain a smooth switch-on and switch-off behaviour of the horizontal output stage the horizontal drive signal is switched-on and off via the soft-start/soft-stop procedure. This function is realised by means of a variation of the TON of the horizontal drive pulse. When the soft-start procedure is completed the horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on during the flyback time. An additional function of the IC is the � low-power start-up�feature. For this function a supply voltage with a value between 3 and 5 V must be available at the start-up pin (required current 5 mA typical). When all sub-address bytes have been sent and the POR and XPR flags have been cleared, the horizontal output can be switched-on via the STB-bit (sub-address 24H). In this condition the horizontal drive signal has the nominal TOFF and the TON grows gradually from zero to the nominal value as indicated in the softstart behaviour. As soon as the 8 V supply is present the switch-on procedure (e.g. closing of the second loop) is continued. The presence of the 8 V supply voltage is indicated by the SUP bit in the I 2 C-bus output byte 02. The circuit generates a vertical sync pulse. This pulse can be selected on pin 49 via the bits CMB1 and CMB0. In the 100 Hz input processor versions the vertical sync pulse is available on pin 63 and the horizontal pulse on pin 56. Via the I C-bus adjustments can be made of the horizontal and vertical geometry. The vertical sawtooth generator drives the vertical output drive circuit, which has a differential output current. For the E-W drive a single ended current output is available. A special feature is the zoom function for both the horizontal and vertical deflection and the vertical scroll function. When the horizontal scan is reduced to display 4 : 3 pictures on a 16 : 9 picture tube an accurate video blanking can be switched on to obtain well-defined edges on the screen. Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When an overvoltage condition is detected the horizontal output drive signal will be switched-off via the slow stop procedure but it is also possible that the drive is not switched-off and that just a protection indication is given in the I 2 C-bus output bytes. The choice is made via the input bit PRD. When PRD = 1 and an overvoltage is detected the drive is switched-off and the STB bit is set to 0. Switching on of the drive is only possible when the XPR flag is cleared. The IC has a second protection input on the j2 filter capacitor pin. When this input is activated the drive signal is switched-off immediately and switched-on again via the slow start procedure. For this reason this protection input can be used as � flash protection� The drive pulses for the vertical sawtooth generator is obtained from a vertical . countdown circuit. This countdown circuit has various windows depending on the incoming signal (50 Hz or 60 Hz and standard or non-standard). The countdown circuit can be forced in various modes by means of the I 2 C-bus. During the insertion of RGB signals the maximum vertical frequency is increased to 72 Hz so that the circuit can also synchronise on signals with a higher vertical frequency like VGA. To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window by means of the NCIN bit. The vertical deflection can be set in the de-interlace mode via the I 2 C bus.

2.5. Chroma and Luminance processing The circuit contains a chroma bandpass and trap circuit. The filters are realised by means of gyrator circuits and they are automatically calibrated by comparing the tuning frequency with the reference frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits. The centre frequency of the chroma bandpass filter is switchable via the I 2 C-bus so that the performance can be optimised for � front-end�signals and external CVBS signals. During SECAM reception the centre frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier frequencies.

2.6. Colour Decoder The colour decoder can decode PAL, NTSC and SECAM signals. The internal clock signals for the various colour standards are generated by means of an internal VCO, which uses the 12 MHz crystal frequency as a reference. Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the colour killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required standard and to activate the FCO-bit (Forced Colour On) in subaddress 21H. The IC contains an